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Making a D Latch for my EE class. The module DL is by my professor and works correctly. The module DLATCH by me does not work. The code is identical.

Does anyone know why? I call them in exactly the same manner in my main module. I've spent about 3 hours trying to find out why.

module DL(input D, E, output reg Q);
reg S, R, QN;
always @(*) begin
S = ~(D & E);
R = ~(~D & E);
Q = ~(R & QN);
QN = ~(S & Q);
end
endmodule

module DLATCH(input D, E, output reg Q);
reg S, R, QN;
always @(*) begin
S = ~(D & E);
R = ~(~D & E);
Q = ~(R & QN);
QN = ~(S & Q);
end
endmodule
Emre
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  • I am testing by hand with a physical board, I will look into what test benches are. – Emre May 17 '22 at 00:52
  • How are the outputs different? A good way to express this would be to include the testbench you are using. If you don't know how to create a testbench see the answer to this SO post. https://stackoverflow.com/questions/20073029/can-anyone-help-me-to-create-a-verilog-testbench – Mikef May 17 '22 at 02:13

0 Answers0