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Which of these activities are performed by the CPU while execution the instructions and which by the Operating System (OS) interrupt handler that manages page faults? I am not sure about the distinction between the two's functions in virtual memory access.

  1. Translate virtual memory address to a physical memory (DRAM) address
  2. Mark a page as recently referenced
  3. If a page is not in DRAM, decide which existing page in DRAM needs to be removed to make room for it
  4. Load a page from disk into DRAM
  5. Update the page table to indicate that the loaded page is now in DRAM
  6. If the program instruction corresponds to a store instruction, indicate in the page table entry that the page is dirty
Peter Cordes
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bloomsdayforever
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  • What do you think and what is your reasoning? – Erik Eidt May 11 '22 at 21:32
  • I think that operating system is responsible for 3,4,5,6 because it decides which page to kick out and update the page in DRAM, but I am not sure about the other ones. – bloomsdayforever May 11 '22 at 21:42
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    (1) is done in hardware b/c the system would barely work at all if software had to get involved in address translation as that happens so regularly. 2 & 6: would be nice if the hardware does it but, software can mark pages so that the OS gets control on first recent read or any write access and so OS can update such status. (If the hardware did 2&6 then TLB entries would effectively have to be written back to the page tables one way or another. I don't know of any hardware that does that, but maybe others do.) – Erik Eidt May 11 '22 at 21:56
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    @ErikEidt: x86 does 2&6 in hardware. https://wiki.osdev.org/Paging Updates of the Accessed or Dirty bits in the PTE [are atomic RMWs](https://stackoverflow.com/questions/69024372/updating-the-pte-bits-from-multiple-cores-how-do-they-avoid-stepping-on-each-o), done in a microcode assist. (Done only if the TLB indicates the bit wasn't already set.) Interesting, I hadn't realized there were many ISAs that *didn't* provide that in HW, but I mostly only know x86, and a bit of MIPS (which does fully software TLB-miss handling.) – Peter Cordes May 11 '22 at 23:12

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