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I'm reading champsim, mainly focusing on CACHE. Now I have a question, does store instructions(e.g. sw in MIPS) only write L1 cache, not really issue dram requests? I think that dram write requests only happen when there is eviction in LLC(last level cache, or maybe L3 cache).

Peter Cordes
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Tokubara
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    That's correct, most CPUs use write-back caches, so DRAM write only happens on eviction from LLC. Once a core has exclusive ownership of a line of L1d cache (MESI E or M state if there are other caches in the system), multiple writes to it are purely a local thing, commit from store buffer to L1d. (Or on a very simple in-order system without a store buffer, directly from a store execution unit.) – Peter Cordes Mar 22 '22 at 02:51

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