Sorry to bother you with a question related to this thread -- I've not the reputation to add a comment there.
The following sequence of events may occur:
- Core2 issues RFOs for both lines. The RFO for line X will complete quickly but the RFO for line Y will have to go all the way to the L3 to invalidate the line in the private caches of core1. Note that core2 can only commit the stores in order, so the store to line X waits until the store to line Y commits.
- Core1 issues the two loads to the L1D. The load from line Y completes quickly, but the load from X requires fetching the line from core2's private caches. Note that the value of Y at this point is zero.
- Line Y is is invalidated from core1's private caches and its state in core2 is changed to a modifiable coherence state.
- Core2 now commits both stores in order.
In this sequence of events Core1 issues the load from line Y before Core2 issues & completes the RFO for the same line. So the sequence of bullets reported does not actually represent the 'time sequence' in which the operations are issued (aka dispatched in Intel terminology).
Does it make sense ? Thanks.
