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In MIPS in clearly specifies that the memory is 8-bit addressable, you can update any 1 address in the 8-bit memory, but words are 32-bits (4 bytes, 4 spots in memory).

Does this mean that the load and save word operation takes 4 cycles? If not, then how is the actually memory designed where you can read and write individual bytes but also 4 at the same time?

Conor OMalley
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  • An aligned word load or store affects 4 bytes at once. [Can modern x86 hardware not store a single byte to memory?](https://stackoverflow.com/q/46721075) talks about systems with caches, where updating an aligned word *in cache* is efficient, and updating one byte of it may be less so on some CPUs. – Peter Cordes Nov 04 '21 at 01:13

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