I'm developing a pipelined NIOS2 microprocessor (part of the Intel FPGA ecosystem) from scratch as a learning exercise. This is a Harvard architecture processor with separate instruction and data memory buses.
When I compile a C case statement GCC creates a jump table and places it directly adjacent to the rest of the executable part of the code. This creates a problem because the processor loads jump table values via the data memory bus, which is not connected to the program memory.
I know in practice the separate memory buses are connected via the cache hierarchy, but I have no cache and I've maintained a strict separation between the two buses.
As a workaround I've made the program memory dual-ported and connected both buses to it, but this doesn't seem like the right solution.
Is there a way for me to direct GCC to separate the jump table and the executable code into different sections? If not, should there be? What's the correct way to be thinking about this issue?
