Verilog gives x output

Question

I've been looking for a solution that allows me to see the output of Q and Qb but can't find it. I'm very new and this is for a college project so I supossed there are a lot of errors.

module TB;
reg [31:0] D;
reg Clk;
wire [31:0] Q, Qb;

Registro f2(D,Clk, Q, Qb);

initial begin

$dumpfile("dump.out");
$dumpvars(0,TB);

        D = 32'b00000000000000000000000000001101; Clk = 1'b0; 
    end
    
initial $monitor("En %2t, D = %b  Q = %b Q' = %b Clk = %b",
                 $time, D, Q, Qb, Clk); 
endmodule 

That's the testbench and I don't think is necessary to give the other modules but just in case:`

module Registro(D,Clk, Q, Qb);

    input [31:0] D;
    input Clk;
    output [31:0] Q,Qb;

    ff_D E0(D[0],Clk,Q[0],Qb[0]);
    ...
    ff_D E31(D[31],Clk,Q[31],Qb[31]);
endmodule


// flip-flop D
module ff_D (D,Clk, Q, Qb);

    input D, Clk;
    output Q, Qb;
    wire a, b, c;
    
    not #(2) n1(c, D);
    and #(3) a1(a, Q, c, Clk);
    and #(3) a2(b, Qb, D, Clk);
    nor #(3) no1(Q, a, Qb);
    nor #(3) no2(Qb, b, Q);

endmodule

I hope someone can help me! Thank you in advance