I'm implementing a function using cpuid in assembly according to AMD64 SysV ABI. I need 2 temporary registers to be used in the function itself: the first one to accumulate return value and the second one as a counter.
My function currently looks as:
;zero argument function
some_cpuid_fun:
push rbx
xor r10d, r10d ;counter initial value
xor r11d, r11d ;return value accumulator initial value
some_cpuid_fun_loop:
;...
cpuid
;update r10d and r11d according to the result
mov eax, r11d
pop rbx
ret
Since cpuid clobbers eax, ebx, ecx, edx I cannot use them across different cpuid executions. As documented in the AMD64 SysV ABI:
r10 temporary register, used for passing a function’s
static chain pointer
r11 temporary register
There is only one strictly temporary register r11, r10 seems to have a different purpose (and its usage as a loop counter is not one, I obviously did not pass any static chain pointers).
QUESTION: Is the some_cpuid_fun function implementation AMD64 SysV ABI compatible? If no how to rewrite it to stay compatible with the ABI?