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For example, could these two instructions begin executing in the same cycle or do they interfere with each other?

MOV  %RAX, (ADDR)      # AT&T syntax: store rax
POP  %RAX
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  • if it's `movl` then shouldn't it be eax? – phuclv Aug 24 '16 at 06:40
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    @LưuVĩnhPhúc: good point, that was totally bogus code. I assuming it was 16-bit Intel-syntax (dst first, WAW hazard), since hardly anybody uses AT&T syntax for 16-bit code. POP AX (`popw %ax`) is valid in 64-bit mode and 32-bit modes, but POPL isn't (and this is tagged x86-64), but I still thought it would be more clear to convert the code to valid 64-bit AT&T syntax. – Peter Cordes Aug 24 '16 at 06:58
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    It was the syntax for Go's assembler, which comes from Plan9 I think. Not the best to use as an example, thanks for changing it. Your rewrite is correct. – Eloff Aug 24 '16 at 14:52

1 Answers1

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Yes, they can execute in the same cycle on a modern out-of-order CPU, because they use Tomasulo's algorithm for register renaming. It totally avoids all write-after-read hazards like this, and also write-after-write, so out-of-order execution is only limited by Read-after-Write true dependencies.

After register renaming, pop will write the new value of the RAX architectural register to a different physical register than the one holding the old value of RAX (which as the input for the store).

The instructions have zero interaction with each other, because the pop starts a new dependency chain for the value of RAX. (Its output is write-only.) The pop (and following instructions that read/write RAX) could be executed many cycles before the store, especially if the value to be stored is produced by a long dependency chain.

See also Agner Fog's microarch pdf and other links in the tag wiki.

update: I thought you were asking about two instructions that write the same register or read the same register, since your original example code left off the % marks, and used AX, so I assume it was 16-bit Intel-syntax. Leaving this part in as a bonus anyway.

Two instructions reading the same register (read-after-read) is not even a hazard at all.

Intel CPUs before Sandybridge have a limitation on the number of not-recently-modified registers that can be read in the same cycle, but reading the same register multiple times in nearby instructions is not a problem. (Search for register read port stalls in Agner Fog's microarch pdf, and/or see this answer where it was relevant).

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