7

At my 64bit Intel machine following code works:

mov rdi, 1 << 40
add r10, rdi

and this quite equivalent looking one produces a warning and doesn't work:

add r10, 1 << 40

Should I just stick with number 1 or am I missing something? This behaviour seems akward.

The warning produced by code nr 2:

warning: signed dword immediate exceeds bounds
Peter Cordes
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user1864035
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  • Related: [How to push a 64bit int in NASM?](https://stackoverflow.com/questions/16917643/how-to-push-a-64bit-int-in-nasm): if a sign-extended imm32 won't work, usually best to `mov` the constant to a register, just like for ALU instructions like `add`. – Peter Cordes Mar 01 '18 at 18:14
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    Also related [`mov r64, imm64` vs. loading it from memory](https://stackoverflow.com/questions/46433208/which-is-faster-imm64-or-m64-for-x86-64). – Peter Cordes Mar 02 '18 at 01:17
  • [x86\_64 Cannot add 64 bit value to rax, "operand mismatch on 'add'"](https://stackoverflow.com/q/58258882) is the GAS version of this; much less helpful error message, but does error instead of warning and encoding a wrong value. – Peter Cordes Oct 10 '20 at 03:34
  • If the value is in memory you can just do a 32-bit add to the high part: `add dword ptr [var + 4], (1 << 40) >> 32` – phuclv Oct 10 '20 at 06:27

1 Answers1

12

There is an opcode for mov r/m64, imm64, but there is no opcode for add r/m64, imm64 in the x86-64 instruction set. In other words: you cannot use 64-bit immediate operand for add, but you can for mov (there are many instructions that don't have the imm64 variant; you can check the Instruction Set Reference in the Intel Software Developer Manual to check which instructions have such variant and which don't).

Griwes
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    In fact `mov` is the *only* instruction that takes an `imm64`. See [Intel's insn set ref manual entry for `mov`](https://github.com/HJLebbink/asm-dude/wiki/MOV). (There's also a special AL/AX/EAX/RAX-only `moffs` form that doesn't use a regular addressing mode, and allows a 64-bit absolute address). But `mov r64, imm64` works with any reg. – Peter Cordes Mar 01 '18 at 18:13