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I'm curious about this, let's say I have:

00000000001 90                              nop        
00000000002 90                              nop        
00000000003 90                              nop

Is it executed exactly the same as this?

00000000001 0F1F00                          nop        dword [ds:rax]

What effect would the second example have as opposed to the first?

Tom Boobas
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    I would be inclined to think the second would execute faster than the first as it's one instruction rather than 3. It's possible that modern pipelining would change that, though. – Loren Pechtel Jul 29 '12 at 04:07
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    Why is this tagged [tag:c]? – Keith Thompson Jul 29 '12 at 04:11
  • Google for multi byte nop, turns up quite a few results. – phant0m Jul 29 '12 at 12:24
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    @KeithThompson - I pulled the C and coding-style tags; they didn't belong. –  Jul 29 '12 at 14:10
  • @phant0m - would you put that comment into an answer and summarize some of the more relevant results? Not all of us have the background to properly understand what would be coming back from that search query. –  Jul 29 '12 at 14:12

2 Answers2

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It depends on the machine architecture. The classic KA-10 (pdp-10) had lots of nop codes, probably a consequence of it's highly regular instruction set, and the fact that it was all implemented by descrete components, not by microcode. Some NOPs referenced memory, some were skip tests that never skipped, but nonetheless tested the condition that might have caused a skip, and so on. "JFCL 0," was advertised in the manual as the fastest nop.

ddyer
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  • I worked on an (8085?) assembler once that offered the option to replace multiple NOPs with a single JMP instruction. You got the alignment you wanted w/o paying the performance penalty. Handy when you had strings in PIC, not so handy if you had CPU-based timing loops (which is why it was off by default). – TMN Jul 30 '12 at 13:17
  • Most times the NOP instruction is used to insert a short delay, usually as a result of some hardware dependency or device errata work around. The performance penalty is the reason for using the NOP. – uɐɪ Jul 30 '12 at 14:00
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    nops have lots of aesoteric uses. Some architectures have byte-alignment requirements for jumps. Self-modifying code (horrors!) used nops as splice points. Bug systems used nops to store information about failed assertions. – ddyer Jul 30 '12 at 20:00
  • @ddyer: Some processors have instructions (sometimes documented, sometimes not) which will fetch a memory byte and either ignore the fetched value completely, or do nothing with it except set flags the programmer may not care about. On the 6502, it was pretty common to use the "BIT abs" instruction as a means of gobbling the next two bytes; there are also some undocumented opcodes which behave similarly except they don't update any flags. One caveat with such tricks, though: they will cause a byte of address space to be read. Some 6502 peripherals may react to read operations. – supercat Sep 18 '12 at 16:59
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It appears that the second example should run quicker than the first. In the first example, three separate instructions will be executed. In the second, only one instruction. The multi-byte NOPs are intended to be used for CPU "hints" (exactly how and when is apparently confidential). They can be useful for alignment purposes (to start a tight loop on a cache line), but currently they have no other use. It's unclear whether the CPU actually evaluates the arguments, so it's not possible to say whether it increases the instruction decoding time or incurs a memory access penalty. Anybody with a good ICE want to test one of these and see what addresses pop up on a bus trace?

TMN
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  • Although many 6502 assemblers use the mnemonic "NOP" for undocumented opcodes which perform a memory fetch (e.g. NOP $1FF9) would be a two-byte instruction which reads address 0x1FF9 and ignores the value read), I would not expect a chip manufacturer to use the term "nop" for an instruction which does anything beyond advance the program counter/instruction pointer since there's no guarantee a processor won't be hooked to hardware which triggers actions (e.g switching to code bank 1) when certain addresses (like 0x1FF9) are accessed, and such triggering isn't exactly "no operation",. – supercat Apr 14 '16 at 15:38