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I remember reading somewhere (maybe on Hacker News or Lobsters) that Motorola made a microprocessor some decades ago with two sets of registers. This means when handling an interrupt, it does not need to do the saving/loading. Does anybody know the name of the microprocessor?

Googling wasn't helpful: it just returns pages after pages of result about Motorola 6800(0), which doesn't seem to have two sets of registers.

Bonus points for explaining why this design didn't go popular. I mean, it sounds like a good idea.

nalzok
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    https://patents.google.com/patent/US4434461 – Bruce Abbott Feb 15 '20 at 01:36
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    Others with similar features = many previous computers. The PDP-11/70 is an example; there were two general register sets, assignable however the kernel wanted. Before that, Atlas had 128 registers and simply reserved (by convention) some of them for interrupt handling. – dave Feb 15 '20 at 03:50
  • More information on this going mainstream: It did sort of catch on, as all ARM based CPU's from the ARM3 onwards have 4 register banks. The User, Supervisor, IRQ and FastIRQ modes, while not switching the entire 16 registers, do switch some of them, I can't remember off the top of my head which ones, but there are different sets for the 4 different modes. – shawty Apr 21 '20 at 12:05
  • The Honeywell 800 had 8 sets - used in round robin fashion by the hardware for multithreading. So the context switch was totally free, woohoo! See here. – davidbak Oct 22 '21 at 03:14

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Sure this is about Motorola? Could it be have been about a similar sounding manufacturer, like Mostek?

Because the first to come to mind would be Zilogs Z80, which was first manufactured by Mostek, as Zilog had no production line of its own. The description about being dedicated to fast interrupt handling is also exactly what the Z80 implementation was about - using the second register set for anything else but a complete swap was rather clumsy.

Of course there were several others with a similar feature (like Valvo's 2650), but none really as much remembered.

As TUM_ mentions, there's a related question about register set usage for the Z80.

Raffzahn
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There is the 6809 which has 2 Stack Pointers, SP and USP (user stack pointer). I think the 68K can manipulate the pointers such that the Stack address can be exchanged with it's other registers.

Neil Cherry
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  • If it helps at all, on the 68k there are eight address registers, each and every one of which can be used as a stack pointer. The only restriction is that exceptions (including interrupts) will always use A7, a particular address register. But it also offers a single instruction to exchange (i.e. swap) the contents of two registers should you want quickly to switch A7 and one of the other As. – Tommy Feb 15 '20 at 23:17
  • If you're making a machine where "user programs" aren't supposed to be able to destroy "the kernel", and there is a hardware stack, then you need a separate stack pointer for the two uses. Otherwise user mode can have a bad stack (bad address in SP, stack full, ….) and the next interrupt will take down the system. But I think of that as a separate thing from having two register sets; I have used machines with 2 SPs and 1 set of "all the other registers". – dave Feb 16 '20 at 02:38
  • The 6809 didn't have that capability to protect memory access. For OS9 and UniFLEX the user programs could access the OS variables. I think the 68000 also had this issue, Starting with the 68010 (68020, and on) there was a built in MMU. – Neil Cherry Feb 16 '20 at 04:39
  • @NeilCherry actually the 6809 could do protected memory with the right extra glue logic. Motorola even made an MMU (6829) for it that did much but not all of the work. – Alan Cox Feb 23 '20 at 00:29
  • @Alan Cox, I wasn't sure of the 6829 having the memory protection, I never had one. It was almost non-existent when I worked with the 6809 in the 80's. Though I did hear a few made it out. – Neil Cherry Feb 23 '20 at 07:38
  • @AlanCox - with the right extra logic, almost any cpu can support memory protection. There were commercial Unix boxes with protected memory on the 8086 in the early 80s. I looked at the feasibility a while back of doing something similar with a Z80 and it seemed reasonably achievable. The basic idea is to maintain a user/supervisor flag externally and only allow switching to supervisor in specific controlled circumstances (Eg on interrupts). Did the 6809 have specific features to make it easier to do this? Both Z80 and 8086 provide a signal whenfetching instructions. Did the 6809 do this? – occipita Apr 24 '20 at 11:01
  • @Occupita, I don't have any of these board but I'm pretty sure there were such add-ons. I think CMS boards have the ability to inject instructions and address information (usually when interrupts occur) and that would vector the CPU to the correct place for a specific device. I think so of the more advamced GIMIX boards had this ability also. I also recall 6502 computers with circuits that could add instructions with TTL. – Neil Cherry Apr 24 '20 at 22:52
  • @occipita 6809 actually makes it quite hard but the GIMIX boards had some of this ability. Z80 is really hard to do but was done (eg MPZ80 board for S-100 systems), later 65C02 and 65C816 have a vector pull so you can tell when an exception is taken so re much easier. The biggest challenge is the stack frame handling on the exception. It's not a co-incidence that processors intended for supervisor/user mode almost all have user and supervisor stack pointers. I'm currently working on a protected mode 65C02 design! – Alan Cox Apr 25 '20 at 17:42