increasing fft size on an embedded implementation

Question

Say I have nRF52840 with 1 MB flash and cortex m4. Assume that I have a vector of $10^5$ int16 samples on which I would like to implement an RFFT. Now, Cimsis-DSP has an implementation for real fft, which for Q1.15 take a maximum input length of 4096. Is there a method to run the full, $10^5$, FFT length?

Answer 1

Is there a method to run the full, $10^5$, FFT length?

Not really. Some reasons:

Not enough memory. The chip has 256kB of RAM. $10^5$ will require 200 kB just to store the input signal. Assuming you want to do something else with the chip as well (e.g. running a Bluetooth interface), you don't have enough RAM. You could try to get creative by using an in-place FFT, storing twiddle factors in Flash, and paging in an out of Flash, but it's going to be a lot of work and highly dependent on what else is happening on the chip.

Long DFTs and limited fixed point precision don't mix well. You will end up with a lot of noise. Consider a Gaussian Noise signal with a max amplitude of 1. If you apply a power conservent FFT (scaling of $\sqrt{N}$ in both directions), the resulting output will also have a max amplitude of about 1 so you only need 1 or two guard bits to avoid clipping. However if you apply the same FFT to a sine wave your max amplitude will be around 160, so you will need at least 9 guard bits. At the same time you'll pick up about 13 dB of numerical noise due to the number of computations so the final signal to noise will be extremely poor.